* The diagram is for providing a high-level overview of my research; it does not cover entire works.
Research Interest
My research interest is mainly in accelerating deep learning and other heavy applications across hardware, compiler mapping, and algorithm. My research interests cover (but not limited to!) the topics I list below:
- Computer Architecture
- Accelerators for deep learning, graph, and so on
- Interconnection networks (NoCs)
- Reconfigurable architecture (CGRA)
- Design automation
- Hardware security
- Compiler
- Dataflow and Mapping in Accelerators
- Data-centric dataflow/mapping representation
- Dataflow – HW co-design
- Machine learning
- Hardware-aware Model Compression
- Model – Dataflow – Accelerator co-design
