Services
Workshop co-organizer (main PoC): Architecture, Compiler, and System Support for Multi-model DNN Workloads Workshop
– 1st (@ MICRO 2021): [Workshop Webpage][Opening Keynote]
– 2nd (@ ISCA 2022): [Workshop Webpage]
Technical Program Committee (TPC): The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC)
2022
External Review Committee: TheACM The International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
2023
External Review Committee: The IEEE/ACM International Symposium on Microarchitecture (MICRO)
2021, 2022
External Review Committee: The International Symposium on Computer Architecture (ISCA)
2021, 2022
Reviewer: IEEE MICRO
2019, 2022
Reviewer: ACM Transactions on Architecture and Code Optimization (TACO)
2019, 2020, 2021
Reviewer: IEEE Transactions on Computers
2019, 2020, 2021
Reviewer: IEEE Computer Architecture Letters (CAL)
2020, 2021
Reviewer: IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
2020
Reviewer: IEEE Transactions on Neural Networks and Learning Systems (TNNLS)
2020
Reviewer: IEEE Open Journal of Circuits and Systems
2020
Talks at Conferences/Workshops
Understanding the Impact of On-Chip Communication on DNN Accelerator Performance
Columbus, Ohio
IEEE/ACM International Symposium on Microarchitecture (MICRO)
Oct. 2019 [Slides]
MAESTRO: An Analytical Cost-Benefit Model of Dataflows in DNN Accelerators
Fukuoka, Japan
ACM Student Research Competition (SRC) at MICRO 2018 (MICRO-SRC) [Final round]
Oct. 2018 [Slides]
MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects
Williamsburg, VA
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
Mar. 2018
Rethinking NoCs for Spatial Neural Network Accelerators
Seoul, Korea
The International Symposium on Networks-on-Chip (NOCS)
Oct. 2017
Adaptive Manycore Architectures for Big Data Computing
Seoul, Korea
The International Symposium on Networks-on-Chip (NOCS)
Oct. 2017
Proving Flow Security of Sequential Logic via Automatically-Synthesized Relational Invariants
Santa Barbara, CA
Computer Security Foundations Symposium (CSF)
Aug. 2017
OpenSMART: Single-cylce Multi-hop NoC Generator in BSV and Chisel
Santa Rosa, CA
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Aug. 2017
Talks in Industry
Understanding Dataflows in DNN Accelerators and Modeling Them with MAESTRO
Online Talk
Sandia National Lab
Dec. 2019
Understanding Dataflows in DNN Accelerators
Menlo Park, California
Facebook
Jun. 2019
An Open Source Framework for Exploring Dataflow and Generating DNN Accelerators Supporting Flexible Dataflow
Yorktown Heights, NY
IBM Research
Nov. 2018
A Communication-driven Approach to Design Flexible DNN Accelerators
Online Talk
Western Digital
Sep. 2018
Cost-benefit Analysis of Application Mappings Strategies in Accelerators
Westford, MA
NVIDIA
Aug. 2018
Optimizing Networks-on-Chip for Deep Learning Accelerators using Micro Switches
Westford, MA
NVIDIA
Aug. 2017
Automatic Generation of Low-latency Networks-on-Chip
Framingham, MA
Bluespec Inc.
Jul. 2017
Talks at Universities (other than Georgia Tech)
Understanding Reuse, Performance, and Hardware Cost of DNN Accelerator Dataflows
Online Invited Talk – AI Seminar Series
Pohang University of Science and Technology (Postech)
Aug. 2020
Understanding Reuse, Performance, and Hardware Cost of DNN Accelerator Dataflows
Seoul, Korea
Seoul National University (SNU)
Jan. 2020
Modeling and Analyzing Dataflows in DNN Accelerators
Tokyo, Japan
Tokyo City University
Dec. 2018
An Open Source Framework for Generating Modular DNN Accelerators
Supporting Flexible Dataflow
Cambridge, MA
Massachusetts Institute of Technology (MIT)
Jul. 2018
A Communication-driven Approach to Design Flexible DNN Accelerators
Pittsburgh, PA
Carnegie Mellon University (CMU)
May. 2018
Designing CNN Accelerators using Bluespec System Verilog
Seoul, Korea
A three-day course for undergraduate students at Seoul National University (SNU)
Dec. 2017
[Slides_Day1][Slides_Day2][Slides_Day3][Lab_Code]
Light-weight and high-performance NoC for DNN Accelerators
Seoul, Korea
Konkuk University
Oct. 2017
Tutorials / Demos
MAERI: An open Source Framework for Generating Modular DNN Accelerators supporting Flexible Dataflow
Washington, D.C.
A tutorial in International Symposium on High-Performance Compute Architecture (HPCA)
Feb. 2019 [Tutorial web page]
MAERI: An open Source Framework for Generating Modular DNN Accelerators supporting Flexible Dataflow
Los Angeles, CA
A tutorial in International Symposium on Compute Architecture (ISCA)
Jun. 2018 [Tutorial web page]
MAESTRO: An Opensource Infrastructure for Modeling Dataflows within Deep Learning Accelerators
Williamsburg, VA
Workshop on Cognitive Architectures (CogArch)
Mar. 2018
OpenSMART: An Opensource Single-cycle Multi-hop NoC Generator
Denver, CO
Workshop on Open Source Supercomputing (OpenSuCo)
Nov. 2017
Hyoukjun Kwon (권혁준) 