MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects
Williamsburg, VA
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
Mar. 2018 (To be presented in the conference)

Designing CNN Accelerators using Bluespec System Verilog
Seoul, Korea
A three-day course for undergraduate students at Seoul National University
Dec. 2017

OpenSMART: An Opensource Single-cycle Multi-hop NoC Generator
Denver, CO
Workshop on Open Source Supercomputing  (OpenSuCo)
Nov. 2017

Rethinking NoCs for  Spatial Neural Network Accelerators
Seoul, Korea
The International Symposium on Networks-on-Chip (NOCS)
Oct. 2017

Adaptive Manycore Architectures for Big Data Computing
Seoul, Korea
The International Symposium on Networks-on-Chip (NOCS)
Oct. 2017

Light-weight and high-performance NoC for DNN Accelerators
Seoul, Korea
Konkuk University

Oct. 2017

Proving Flow Security of Sequential Logic via Automatically-Synthesized Relational Invariants
Santa Barbara, CA
Computer Security Foundations Symposium (CSF)
Aug. 2017

Optimizing Networks-on-Chip for Deep Learning Accelerators using Micro-switches
Westford, MA
Aug. 2017

Automatic Generation of Low-latency Networks-on-Chip
Framingham, MA
Bluespec Inc.
Jul. 2017

OpenSMART: Single-cylce Multi-hop NoC Generator in BSV and Chisel
Santa Rosa, CA
International Symposium on Performance Analysis of Systems and Software (ISPASS)
Aug. 2017